|
03.02.2005 23:13:00
|
System Co-Design is Key for Greater Electronics Miniaturization
System Co-Design is Key for Greater Electronics Miniaturization Technology Leaders at the 2005 SiP Technology Symposium in Tokyo, Japan Identify Co-Design as a Key Enabler of Continued Product Innovation
During the 1st Annual SiP Technology Symposium held on January 18 in Tokyo, Japan, key executives and technologists from leading U.S. and Japanese semiconductor companies shared their perspectives on achieving greater electronics miniaturization and performance through advanced electronics packaging. Speakers from companies spanning the semiconductor supply chain -- including Elpida, Hitachi Cable, IBM, Spansion and others -- explored how to leverage System-in-Package (SiP) and other technologies to meet the product and business challenges facing the industry today.
The need for system co-design emerged as a consistent theme throughout the half-day event, as industry leaders called for greater collaboration at every stage of the design process. The event was held on Tuesday, January 18 at the Meridien Grand Pacific Hotel in Tokyo. Tessera (Nasdaq:TSRA) and Semiconductor International Japan teamed to co-sponsor the event.
David Tuckerman, Tessera's chief technical officer, kicked off the event with a keynote address on lowering the risk of SiP implementation. Tuckerman stated that in many cases, SiP implementation is often less risky than system-on-chip (SOC) implementation. The use of the package's 3rd dimension is critical to the development of novel electronic products, such as personal digital assistants (PDAs) that can take the form factor of a pen.
Henry Utsunomiya, president of Interconnection Technologies, provided an overview of market trends and applications for multiple-die packaging and echoed the key themes of the event, calling for enhanced cooperation between electronic product manufacturers, semiconductor manufacturers and materials suppliers to support the development of next-generation electronic products.
Craig Mitchell, vice president of marketing at Tessera, presented a new design methodology referred to as SLIM, for system-level integration and miniaturization. SLIM-designed systems eliminate unnecessary levels of interconnect and take full advantage of the packaging and interconnect technologies currently available to achieve significant size reductions while enhancing product performance.
3D design tools and advanced substrates were identified as key building blocks of SiP systems throughout the symposium. Gordon Jensen, president of CAD Design Software, introduced a 3D design tool with a manufacturing feedback system that allows complex 3D packages to be readily designed and optimized for volume manufacturing. Kimitaka Endo, manager of the R&D division at North, discussed North's copper-bump interconnect technology, which can be used to create high-density, multi-layer substrates. Hiroyuki Okabe, technical manager at Hitachi Cable, commented that flex-based substrates can deliver high density, thin profile, high reliability and low cost, key requirements in advanced consumer, wireless and computing electronics.
Spansion's Junichi Kasai, vice president of final manufacturing R&D, reviewed the main challenges facing Spansion when integrating logic and memory devices in the footprint of a single package. He discussed a 3D virtual design system that Spansion is utilizing to help address the design, cost and time-to-market challenges associated with mixed-device type integration.
Ichiro Anjo, Elpida Memory's senior manager, production engineering department, commented that as DRAM chips move toward higher speeds, they will need to be packaged in FBGAs. With this shift in packaging, new stacking technology will also be required to meet the increasing demand in next-generation products. He went on to review a number of stacking techniques, which could be leveraged to meet this demand.
IBM's Jonathan Hinkle, design engineer, discussed the need for advanced packaging in blade server applications to meet high-density memory requirements. One such example involves the combination of package-stacking technology in a new format memory module called a VLP (very low profile)-DIMM. This combination results in a 62-percent reduction in the board space required in a blade server's memory subsystem.
Joseph Fjelstad, co-founder of Silicon Pipe, reviewed the topic of emerging trends in advanced IC packaging and interconnection for high-speed applications. He explored an innovative copper-based interconnect technology designed to close the 10x interconnect gap between signal speeds on ICs and PC boards.
Kenji Tsuda, editor of Semiconductor International Japan, provided closing comments for the Symposium, stating that the digital consumer is driving Japanese growth. He commented that Japanese semiconductor companies should continue to enhance their communications and collaboration in the global marketplace to remain competitive and retain a leadership position.
At the end of the day, presenters echoed the sentiment that co-design and elevated dialogue and cooperation are needed to develop next-generation electronic products that optimally leverage a diverse range of technologies. Copies of the Symposium proceedings are available for $35.00. To order, contact Daryl Larsen, Symposium event manager, at (408) 952-4364 or dlarsen@tessera.com.
About Tessera, Inc.
Tessera is a leading provider of miniaturization technologies for the electronics industry. Tessera enables new levels of miniaturization and performance by applying its unique expertise in the electrical, thermal and mechanical properties of materials and interconnect. As a result, Tessera's technologies are widely adopted in high-growth markets including consumer, computing, communications, medical and defense. Tessera's customers include the world's top semiconductor companies such as Intel, Samsung, Renesas, Toshiba and Texas Instruments. The company's stock is traded on the Nasdaq National Market under the symbol TSRA. Tessera is headquartered in San Jose, California. www.tessera.com.
Safe Harbor Statement
This press release contains forward-looking statements, which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward-looking statements involve risks and uncertainties that could cause actual results to differ significantly from those projected. Factors that might cause or contribute to such differences include, but are not limited to, fluctuations in Tessera's operating results due to the timing of new license agreements and royalties, the pace of adoption of Tessera's chip scale and multi-chip packaging technologies by the consumer electronics industry, Tessera's ability to protect its intellectual property and increases in the costs of that effort and the risk of a decline in demand for semiconductor products. You are cautioned not to place undue reliance on the forward-looking statements, which speak only as of the date of this release. Tessera's filings with the Securities and Exchange Commission, including its Annual Report on Form 10-K for the year ended December 31, 2003 and its Quarterly Report on Form 10-Q filed for the quarter ended September 30, 2004, include more information about factors that could affect the company's financial results.
Note: Tessera and the Tessera logo are registered trademarks of Tessera, Inc. All other company, brand and product names may be trademarks or registered trademarks of their respective companies.
--30--EB/sf*
Business Editors/Technology Editors
SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 3, 2005--
During the 1st Annual SiP Technology Symposium held on January 18 in Tokyo, Japan, key executives and technologists from leading U.S. and Japanese semiconductor companies shared their perspectives on achieving greater electronics miniaturization and performance through advanced electronics packaging. Speakers from companies spanning the semiconductor supply chain -- including Elpida, Hitachi Cable, IBM, Spansion and others -- explored how to leverage System-in-Package (SiP) and other technologies to meet the product and business challenges facing the industry today.
The need for system co-design emerged as a consistent theme throughout the half-day event, as industry leaders called for greater collaboration at every stage of the design process. The event was held on Tuesday, January 18 at the Meridien Grand Pacific Hotel in Tokyo. Tessera (Nasdaq:TSRA) and Semiconductor International Japan teamed to co-sponsor the event.
David Tuckerman, Tessera's chief technical officer, kicked off the event with a keynote address on lowering the risk of SiP implementation. Tuckerman stated that in many cases, SiP implementation is often less risky than system-on-chip (SOC) implementation. The use of the package's 3rd dimension is critical to the development of novel electronic products, such as personal digital assistants (PDAs) that can take the form factor of a pen.
Henry Utsunomiya, president of Interconnection Technologies, provided an overview of market trends and applications for multiple-die packaging and echoed the key themes of the event, calling for enhanced cooperation between electronic product manufacturers, semiconductor manufacturers and materials suppliers to support the development of next-generation electronic products.
Craig Mitchell, vice president of marketing at Tessera, presented a new design methodology referred to as SLIM, for system-level integration and miniaturization. SLIM-designed systems eliminate unnecessary levels of interconnect and take full advantage of the packaging and interconnect technologies currently available to achieve significant size reductions while enhancing product performance.
3D design tools and advanced substrates were identified as key building blocks of SiP systems throughout the symposium. Gordon Jensen, president of CAD Design Software, introduced a 3D design tool with a manufacturing feedback system that allows complex 3D packages to be readily designed and optimized for volume manufacturing. Kimitaka Endo, manager of the R&D division at North, discussed North's copper-bump interconnect technology, which can be used to create high-density, multi-layer substrates. Hiroyuki Okabe, technical manager at Hitachi Cable, commented that flex-based substrates can deliver high density, thin profile, high reliability and low cost, key requirements in advanced consumer, wireless and computing electronics.
Spansion's Junichi Kasai, vice president of final manufacturing R&D, reviewed the main challenges facing Spansion when integrating logic and memory devices in the footprint of a single package. He discussed a 3D virtual design system that Spansion is utilizing to help address the design, cost and time-to-market challenges associated with mixed-device type integration.
Ichiro Anjo, Elpida Memory's senior manager, production engineering department, commented that as DRAM chips move toward higher speeds, they will need to be packaged in FBGAs. With this shift in packaging, new stacking technology will also be required to meet the increasing demand in next-generation products. He went on to review a number of stacking techniques, which could be leveraged to meet this demand.
IBM's Jonathan Hinkle, design engineer, discussed the need for advanced packaging in blade server applications to meet high-density memory requirements. One such example involves the combination of package-stacking technology in a new format memory module called a VLP (very low profile)-DIMM. This combination results in a 62-percent reduction in the board space required in a blade server's memory subsystem.
Joseph Fjelstad, co-founder of Silicon Pipe, reviewed the topic of emerging trends in advanced IC packaging and interconnection for high-speed applications. He explored an innovative copper-based interconnect technology designed to close the 10x interconnect gap between signal speeds on ICs and PC boards.
Kenji Tsuda, editor of Semiconductor International Japan, provided closing comments for the Symposium, stating that the digital consumer is driving Japanese growth. He commented that Japanese semiconductor companies should continue to enhance their communications and collaboration in the global marketplace to remain competitive and retain a leadership position.
At the end of the day, presenters echoed the sentiment that co-design and elevated dialogue and cooperation are needed to develop next-generation electronic products that optimally leverage a diverse range of technologies. Copies of the Symposium proceedings are available for $35.00. To order, contact Daryl Larsen, Symposium event manager, at (408) 952-4364 or dlarsen@tessera.com.
About Tessera, Inc.
Tessera is a leading provider of miniaturization technologies for the electronics industry. Tessera enables new levels of miniaturization and performance by applying its unique expertise in the electrical, thermal and mechanical properties of materials and interconnect. As a result, Tessera's technologies are widely adopted in high-growth markets including consumer, computing, communications, medical and defense. Tessera's customers include the world's top semiconductor companies such as Intel, Samsung, Renesas, Toshiba and Texas Instruments. The company's stock is traded on the Nasdaq National Market under the symbol TSRA. Tessera is headquartered in San Jose, California. www.tessera.com.
Safe Harbor Statement
This press release contains forward-looking statements, which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward-looking statements involve risks and uncertainties that could cause actual results to differ significantly from those projected. Factors that might cause or contribute to such differences include, but are not limited to, fluctuations in Tessera's operating results due to the timing of new license agreements and royalties, the pace of adoption of Tessera's chip scale and multi-chip packaging technologies by the consumer electronics industry, Tessera's ability to protect its intellectual property and increases in the costs of that effort and the risk of a decline in demand for semiconductor products. You are cautioned not to place undue reliance on the forward-looking statements, which speak only as of the date of this release. Tessera's filings with the Securities and Exchange Commission, including its Annual Report on Form 10-K for the year ended December 31, 2003 and its Quarterly Report on Form 10-Q filed for the quarter ended September 30, 2004, include more information about factors that could affect the company's financial results.
Note: Tessera and the Tessera logo are registered trademarks of Tessera, Inc. All other company, brand and product names may be trademarks or registered trademarks of their respective companies.
--30--EB/sf*
CONTACT: Tessera Joyce Smaragdis, 408-952-4317 jsmaragdis@tessera.com or Porter Novelli Ricky Gradwohl, 408-369-4600 x631 ricky.gradwohl@porternovelli.com
KEYWORD: CALIFORNIA JAPAN INTERNATIONAL ASIA PACIFIC INDUSTRY KEYWORD: HARDWARE SOFTWARE COMPUTERS/ELECTRONICS NETWORKING SOURCE: Tessera, Inc.
Copyright Business Wire 2005
Der finanzen.at Ratgeber für Aktien!
Wenn Sie mehr über das Thema Aktien erfahren wollen, finden Sie in unserem Ratgeber viele interessante Artikel dazu!
Jetzt informieren!
JETZT DEVISEN-CFDS MIT BIS ZU HEBEL 30 HANDELN
Handeln Sie Devisen-CFDs mit kleinen Spreads. Mit nur 100 € können Sie mit der Wirkung von 3.000 Euro Kapital handeln.
82% der Kleinanlegerkonten verlieren Geld beim CFD-Handel mit diesem Anbieter. Sie sollten überlegen, ob Sie es sich leisten können, das hohe Risiko einzugehen, Ihr Geld zu verlieren.
Nachrichten zu Tessera Technologies Inc.mehr Nachrichten
| Keine Nachrichten verfügbar. |
Analysen zu Tessera Technologies Inc.mehr Analysen
ETF-Sparplan
Oskar ist der einfache und intelligente ETF-Sparplan. Er übernimmt die ETF-Auswahl, ist steuersmart, transparent und kostengünstig.